1. Technical Field
The present invention generally relates to processor design and in particular to computation units employing floating point operands within a processor. Still more particularly, the present invention relates to floating point convert to integer operations within a processor.
2. Description of the Related Art
Number conversion from fixed point format to floating point format and vice versa occurs with sufficient frequency within processors to justify inclusion of conversion instructions within an instruction set architecture (ISA). For example, floating point convert to integer (fcti) instructions are supported in the instruction set architecture of the PowerPC family of processors.
When precision is lost during conversion of a floating point number to a fixed point number, the result of the conversion is rounded under the influence of the current rounding mode. In most floating point designs, the determination of whether to increment the result of a floating point operation due to rounding (followed by storing the result into a register file) is a persistent critical path. This determination of whether to increment the result due to rounding must necessarily occur near the end of execution of a floating point operation. Including support for rounding of floating point convert to integer results within the rounding mechanism for floating point operation results (to allow reuse of that mechanism in floating point convert to integer operations) further impacts this already critical path since floating point convert to integer operations present different computational requirements than floating point operations.
The impact on the critical path may be alleviated by adding a processor cycle to the execution latency, but not without degrading performance. It would be desirable, therefore, to provide a computational system for rounding the result of floating point convert to integer operations utilizing only the minimum logic required for execution of standard floating point operations without significantly degrading performance.
It is therefore one object of the present invention to provide an improved processor design.
It is another object of the present invention to provide an improved design for computation units employing floating point operands within a processor.
It is yet another object of the present invention to provide improving performance of floating point convert to integer operations within a processor.
The foregoing objects are achieved as is now described. During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.